$NOMOD51

;   *** <<< Use Configuration Wizard in Context Menu >>> ***
;
ROM_SIZE        EQU     0x8000      ;   32K
;
; <h> Clock Initialization
;   <o.0>       LSEL        <0x00=> LRC     <0x01=> LXT
LSEL            EQU     0x00
;   <o.1..2>    HSEL        <0x00=> HRC     <0x01=> MXT     <0x02=> HXT
HSEL            EQU     0x02  
;   <o.4..5>    LXT_ENH     <0x00=> Low     <0x01=> Middle  <0x03=> High
LXT_ENH         EQU     0x30
; </h>
;
; <h> Watch Dog Timer Initialization
;   <o.0>       WDTDIS      <0x00=> Program Control     <0x01=> Disable
WDTDIS          EQU     0x00
;   <o.1>       WDTMODE     <0x00=> Reset               <0x01=> Interrupt
WDTMODE         EQU     0x00
;   <o.2>       WDTSMODE    <0x00=> Reset               <0x01=> Interrupt
WDTSMODE        EQU     0x04
; </h>
;
; <h> Low Voltage Reset Initialization
;   <o.0>       LVRON       <0x00=> Program Control     <0x01=> Enable
LVRON           EQU     0x00
;   <o.1..4>    LVRVOL      <0x00=> 1.6V    <0x01=> 1.8V    <0x02=> 2.0V    <0x03=> 2.2V    <0x04=> 2.4V    <0x05=> 2.7V    <0x06=> 3.0V    <0x07=> 3.3V    <0x08=> 3.6V    <0x09=> 4.2V
LVRVOL          EQU     0x00
; </h>
;
; <h> Low Voltage Reset Initialization
;  <o> Flash Sector 0 ~ 7 Write Protect                <0-255>
FSWP_0_7        EQU     0xFF
;  <o> Flash Sector 8 ~ 15 Write Protect               <0-255>
FSWP_8_15       EQU     0xFF
;  <o> Flash Sector 16 ~ 23 Write Protect              <0-255>
FSWP_16_23      EQU     0xFF
;  <o> Flash Sector 24 ~ 31 Write Protect              <0-255>
FSWP_24_31      EQU     0xFF
;  <o> Flash Sector 32 ~ 39 Write Protect              <0-255>
FSWP_32_39      EQU     0xFF
;  <o> Flash Sector 40 ~ 47 Write Protect              <0-255>
FSWP_40_47      EQU     0xFF
;  <o> Flash Sector 48 ~ 55 Write Protect              <0-255>
FSWP_48_55      EQU     0xFF
;  <o> Flash Sector 56 ~ 63 Write Protect              <0-255>
FSWP_56_63      EQU     0xFF
;  <o> NVR Sector 0 ~ 7 Write Protect                  <0-255>
NVRWP_0_7       EQU     0xFF
;  <o> NVR Sector 8 ~ 13 Write Protect                 <0-63>
NVRWP_8_13      EQU     0xFF
; </h>
;  
; <h> Program JTAG and Encryption
;   <o.0..1>       ENCRYP    <0x00=> Both    <0x01=> ENCRYP JTAG 1    <0x02=> ENCRYP JTAG 2    <0x03=> Disable 
ENCRYP          EQU     0x03
;   <o.4..5>       JTAG    <0x00=> Disable1    <0x01=> Disable2    <0x02=> PB    <0x03=> PC 
JTAG          EQU     0x20

; </h>

CSEG            AT      0x7F00
DB              0x4C
DB              0x4E
DB              ENCRYP + JTAG
DB              NVRWP_0_7
DB              NVRWP_8_13
DB              FSWP_0_7
DB              FSWP_8_15
DB              FSWP_16_23
DB              FSWP_24_31
DB              FSWP_32_39
DB              FSWP_40_47
DB              FSWP_48_55
DB              FSWP_56_63
DB              LVRVOL + LVRON
DB              WDTDIS + WDTMODE + WDTSMODE
DB              LSEL + HSEL + LXT_ENH
;------------------------------------------------------------------------------
;
;  User-defined <h> Power-On Initialization of Memory
;
;  With the following EQU statements the initialization of memory
;  at processor reset can be defined:
;
; <o> IDATALEN: IDATA memory size <0x0-0x100>
;     <i> Note: The absolute start-address of IDATA memory is always 0
;     <i>       The IDATA space overlaps physically the DATA and BIT areas.
IDATALEN        EQU     100H
;
; <o> XDATASTART: XDATA memory start address <0x0-0xFFFF> 
;     <i> The absolute start address of XDATA memory
XDATASTART      EQU     0     
;
; <o> XDATALEN: XDATA memory size <0x0-0xFFFF> 
;     <i> The length of XDATA memory in bytes.
XDATALEN        EQU     400H      
;
; <o> PDATASTART: PDATA memory start address <0x0-0xFFFF> 
;     <i> The absolute start address of PDATA memory
PDATASTART      EQU     0H
;
; <o> PDATALEN: PDATA memory size <0x0-0xFF> 
;     <i> The length of PDATA memory in bytes.
PDATALEN        EQU     0H
;
;</h>
;------------------------------------------------------------------------------
;
;<h> Reentrant Stack Initialization
;
;  The following EQU statements define the stack pointer for reentrant
;  functions and initialized it:
;
; <h> Stack Space for reentrant functions in the SMALL model.
;  <q> IBPSTACK: Enable SMALL model reentrant stack
;     <i> Stack space for reentrant functions in the SMALL model.
IBPSTACK        EQU     0       ; set to 1 if small reentrant is used.
;  <o> IBPSTACKTOP: End address of SMALL model stack <0x0-0xFF>
;     <i> Set the top of the stack to the highest location.
IBPSTACKTOP     EQU     0xFF + 1     ; default 0FFH+1  
; </h>
;
; <h> Stack Space for reentrant functions in the LARGE model.      
;  <q> XBPSTACK: Enable LARGE model reentrant stack
;     <i> Stack space for reentrant functions in the LARGE model.
XBPSTACK        EQU     0       ; set to 1 if large reentrant is used.
;  <o> XBPSTACKTOP: End address of LARGE model stack <0x0-0xFFFF>
;     <i> Set the top of the stack to the highest location.
XBPSTACKTOP     EQU     0xFFFF + 1   ; default 0FFFFH+1 
; </h>
;
; <h> Stack Space for reentrant functions in the COMPACT model.    
;  <q> PBPSTACK: Enable COMPACT model reentrant stack
;     <i> Stack space for reentrant functions in the COMPACT model.
PBPSTACK        EQU     0       ; set to 1 if compact reentrant is used.
;
;   <o> PBPSTACKTOP: End address of COMPACT model stack <0x0-0xFFFF>
;     <i> Set the top of the stack to the highest location.
PBPSTACKTOP     EQU     0xFF + 1     ; default 0FFH+1  
; </h>
;</h>
;------------------------------------------------------------------------------
;
;  Memory Page for Using the Compact Model with 64 KByte xdata RAM
;  <e>Compact Model Page Definition
;
;  <i>Define the XDATA page used for PDATA variables. 
;  <i>PPAGE must conform with the PPAGE set in the linker invocation.
;
; Enable pdata memory page initalization
PPAGEENABLE     EQU     1       ; set to 1 if pdata object are used.
;
; <o> PPAGE number <0x0-0xFF> 
; <i> uppermost 256-byte address of the page used for PDATA variables.
PPAGE           EQU     0
;
; <o> SFR address which supplies uppermost address byte <0x0-0xFF> 
; <i> most 8051 variants use P2 as uppermost address byte
PPAGE_SFR       DATA    0A0H
;
; </e>
;------------------------------------------------------------------------------

; Standard SFR Symbols 
ACC     DATA    0E0H
B       DATA    0F0H
SP      DATA    81H
DPL     DATA    82H
DPH     DATA    83H

                NAME    ?C_STARTUP


?C_C51STARTUP   SEGMENT   CODE
?STACK          SEGMENT   IDATA

                RSEG    ?STACK
                DS      1

                EXTRN CODE (?C_START)
                PUBLIC  ?C_STARTUP

                CSEG    AT      0
?C_STARTUP:     LJMP    STARTUP1

                RSEG    ?C_C51STARTUP

STARTUP1:

IF IDATALEN <> 0
                MOV     R0,#IDATALEN - 1
                CLR     A
IDATALOOP:      MOV     @R0,A
                DJNZ    R0,IDATALOOP
ENDIF

IF XDATALEN <> 0
                MOV     DPTR,#XDATASTART
                MOV     R7,#LOW (XDATALEN)
  IF (LOW (XDATALEN)) <> 0
                MOV     R6,#(HIGH (XDATALEN)) +1
  ELSE
                MOV     R6,#HIGH (XDATALEN)
  ENDIF
                CLR     A
XDATALOOP:      MOVX    @DPTR,A
                INC     DPTR
                DJNZ    R7,XDATALOOP
                DJNZ    R6,XDATALOOP
ENDIF

IF PPAGEENABLE <> 0
                MOV     PPAGE_SFR,#PPAGE
ENDIF

IF PDATALEN <> 0
                MOV     R0,#LOW (PDATASTART)
                MOV     R7,#LOW (PDATALEN)
                CLR     A
PDATALOOP:      MOVX    @R0,A
                INC     R0
                DJNZ    R7,PDATALOOP
ENDIF

IF IBPSTACK <> 0
EXTRN DATA (?C_IBP)

                MOV     ?C_IBP,#LOW IBPSTACKTOP
ENDIF

IF XBPSTACK <> 0
EXTRN DATA (?C_XBP)

                MOV     ?C_XBP,#HIGH XBPSTACKTOP
                MOV     ?C_XBP+1,#LOW XBPSTACKTOP
ENDIF

IF PBPSTACK <> 0
EXTRN DATA (?C_PBP)
                MOV     ?C_PBP,#LOW PBPSTACKTOP
ENDIF

                MOV     SP,#?STACK-1

; This code is required if you use L51_BANK.A51 with Banking Mode 4
;<h> Code Banking
; <q> Select Bank 0 for L51_BANK.A51 Mode 4
#if 0   
;     <i> Initialize bank mechanism to code bank 0 when using L51_BANK.A51 with Banking Mode 4.
EXTRN CODE (?B_SWITCH0)
                CALL    ?B_SWITCH0      ; init bank mechanism to code bank 0
#endif
;</h>
                LJMP    ?C_START

                END
